32MB EDO Printer Memory, 60ns, MT4LDT832UG-6X, OEM (модуль памяти)

32MB EDO Printer Memory, 60ns, MT4LDT832UG-6X

Datasheet text preview:
4, 8 MEG x 32 DRAM DIMMs
DRAM MODULE
FEATURES
· JEDEC pinout in a 100-pin, dual in-line memory module (DIMM) · 16MB (4 Meg x 32) and 32MB (8 Meg x 32) · High-performance CMOS silicon-gate process · Single +3.3V ±0.3V power supply · All inputs, outputs and clocks are TTL-compatible · 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms · FAST-PAGE-MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles · Serial presence-detect (SPD)
MT2LDT432U (X), MT4LDT832U (X)
GENERAL DESCRIPTION
The MT2LDT432U (X) and MT4LDT832U (X) are randomly accessed 16MB and 32MB memories organized in a x32 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each location is uniquely addressed via the address bits. The row address is latched by the RAS# signal, then the column address is latched by the CAS# signal. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. F A S T - P A G E - M O D E modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO operates as any DRAM READ or FAST-PAGE-MODE READ, except data will be held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. (Refer to the 4 Meg x 16 [MT4LC4M16R6] DRAM data sheet for additional information on EDO functionality.)
REFRESH
Memory cell data is retained in its correct state by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data operations (READ or WRITE) within a row-addressdefined page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGEMODE operation.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM's SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/ EEPROM addresses.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" option, is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs.